Tech Blog – 8520 Complex Interface Adapter Specification
1.0 Description/Part #318029-01
The complex interface adapter (CIA) is a 65xx Bus compatible peripherial interface device with extremely flexible timing and I/O capabilities. See Figure 2 for block diagram.
1.1 Configuration
The CIA shall come in a standard 40 pin package. See Figure 1 for pin configuration.
1.2 Sources
See approved vendor's list for approved sources.
1.3 Interface Signals
1.3.1 02 – Clock Input
The 02 clock is a TTL compatible input used for internal device operation and as a timing reference for communicating with the system data bus.
1.3.2 CS – Chip Select Input
The CS input controls the activity of the 8520. A low level on CS while 02 is high, causes the device to respond to signals on the R/W and address (RS) lines. A high on CS prevents these lines from controlling the 8520. The CS line is normally activated (low) at 02 by the appropriate address combination.
1.3.3 R/W – Read/Write Input
The R/W signal is normally supplied by the microprocessor and controls the direction of data transfers of the 8520. A high on R/W indicates a read (data transfer out of 8520), while a low indicates a write (data transfer into the 8520).
1.3.4 RS0-RS3 – Address Inputs
The address inputs select the internal registers as described by the Register Map.
1.3.5 DB7-DB0 – Data Bus Inputs/Outputs
The eight bit data bus transfers information between the 8520 and the system data bus. These pins are high impedance inputs unless CS is low and R/W and 02 are high, to read the device. During this read, the data bus output buffers are enabled, driving the data from the selected register onto the system data bus.
1.3.6 IRQ – Interrupt Request Output
IRQ is an open drain output normally connected to the processor interrupt input. An external pullup resistor holds the signal high, allowing multiple IRQ outputs to be connected together. The IRQ output is normally off (high impedance) and is activated low as indicated in the functional description.
1.3.7 RES – Reset Input
A low on the RES pin resets all internal registers. The port pins are set as inputs and port registers to zero (although a read on the ports will return all highs because of passive pullups). The timer control registers are set to zero and the timer latches to all ones. All other registers are reset to zero.
1.4 Register Map
RS3 | RS2 | RS1 | RS0 | REG | Description |
---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | PRA – Peripherial Data Register A |
0 | 0 | 0 | 1 | 1 | PRB – Peripherial Data Register B |
0 | 0 | 1 | 0 | 2 | DDRA – Data Direction Register A |
0 | 0 | 1 | 1 | 3 | DDRB – Data Direction Register B |
0 | 1 | 0 | 0 | 4 | TA LO – Timer A Low Register |
0 | 1 | 0 | 1 | 5 | TA HI – Timer A High Register |
0 | 1 | 1 | 0 | 6 | TB LO – Timer B Low Register |
0 | 1 | 1 | 1 | 7 | TB HI – Timer B High Register |
1 | 0 | 0 | 0 | 8 | Event LSB |
1 | 0 | 0 | 1 | 9 | Event 8-15 |
1 | 0 | 1 | 0 | A | Event MSB |
1 | 0 | 1 | 1 | B | No Connect |
1 | 1 | 0 | 0 | C | SDR – Serial Data Register |
1 | 1 | 0 | 1 | D | ICR – Interrupt Control Register |
1 | 1 | 1 | 0 | E | CRA – Control Register A |
1 | 1 | 1 | 1 | F | CRB – Control Register B |
1.5 Functional Description
1.5.1 I/O Ports (PRA, PRB, DDRA, DDRB)
Ports A and B each consist of an 8-bit Peripherial Data Register (PR) and an 8-bit Data Direction Register (DDR). If a bit in the DDR is set, the corresponding bit in the PR is an output. If a DDR bit is set to zero, the corresponding PR bit is defined as an input. On a read, the PR reflects the information present on the actual port pins (PA0-PA7, PB0-PB7) for both input and output bits. PORT A has both passive and active pullup devices, providing both CMOS and TTL compatibility. It can drive 2 TTL loads. PORT B has only passive pullup devices and has a much higher current-sinking capability.
1.5.2 Handshaking
Handshaking on data transfers can be accomplished using the PC output pin and the FLAG input pin. PC will go low on the third cycle after a PORT B access. This signal can be used indicate "data ready" at PORT B or "data accepted" from PORT B. Handshaking on a 16-bit data transfers (using both PORT A and PORT B) is possible by always reading or writing PORT A first. FLAG is a negative edge sensitive input, which can be used for receiving the PC output from another 8520 or as a general purpose interrupt input.
1.5.3 Interval Timers (Timer A, Timer B)
Each interval timer consists of a 16-bit read-only Timer Counter and a 16-bit write-only Timer Latch. Data written to the timer are latched in the Timer Latch, while data read from the timer are the present contents of the Timer Counter. The timers can be used independently or linked for extended operations. The various timer modes allow generation of long time delays, variable width pulses, pulse trains and variable frequency waveforms. Utilizing the CNT input, the timers can count external pulses or measure frequenct, pulse width and delay times of external signals. Each timer has an associated control register, providing independent control of the following functions:
1.5.4 Start/Stop
A control bit allows the timer to be started or stopped by the microprocessor at any time.
1.5.5 PB On/Off
A control bit allows the timer output to appear on a PORT B output line (PB6 for TIMER A and PB7 for TIMER B). This function overrides the DDRB control bit and forces the appriopriate PB line to an output.
1.5.6 Toggle/Pulse
A control bit selects the output applied to PORT B. On every timer underflow the output can either toggle or generate a single positive pulse of one cycle duration. The toggle output is set high whenever the timer is started and is set low by RES.
1.5.7 One-Shot/Continuous
A control bit selects either timer mode. In one-shot mode, the timer will count down from the latched value to zero, generate an interrupt, reload the latched value, then stop. In continuous mode, the timer will count from the latched value to zero, generate an interrupt, reload the latched value and repeat the procedure continuously. In one-shot mode a write to Timer High (registers 5 for TIMER A, 7 for TIMER B) will transfer the timer latch to the counter and initiate counting regardless of the start bit.
1.5.8 Force Load
A strobe bit allows the timer latch to be loaded into the timer counter at any time, whether the time is running or not.
1.5.9 Input Mode
Control bits allow selection of the clock used to decrement the timer. TIMER A can count 02 pulses or external pulses applied to the CNT pin. TIMER B can count 02 pulses, external CNT pulses, TIMER A underflow pulses or TIMER A underflow pulses while the CNT pin is held high.
The timer latch is loaded into the timer on any timer underflow, on a force load or following a write to the high byte of the prescaler while the timer is stopped. If the timer is running, a write to the high byte will load the timer latch, but not reload the counter.
1.5.10 TOD
TOD consists of a 24-bit binary counter. Positive edge transitions on this pin cause the binary counter to increment. The TOD pin has a passive pull-up on it. A programmable ALARM is provided for generating an interrupt at a desired time. The ALARM registers are located at the same addresses as the corresponding TOD register. Access to the ALARM is governed by a Control Register bit. The ALARM is write only; any read of a TOD address will read time regardless of the state of the ALARM access bit.
A specific sequence of events must be followed for proper setting and reading of TOD. TOD is automatically stopped whenever a write to the register occurs. The clock will not start again until after a write to the LSB Event Register. This assures TOD will always start at desired time. Since a carry from one stage to the next can occur at any time with respect to a read operation, a latching function is included to keep all Time of Day information constant during a read sequence. All TOD registers latch on a read of MSB event and remain latched until after a read of LSB event. The TOD clock continues to count when the output registers are latched. If only one register is to be read, there is no carry problem and the register can be read "on the fly", provided that any read of MSB Event is followed by a read of LSB Event to disable the latching.
1.5.11 Serial Port
The serial port is a buffered, 8-bit synchronous shift register system. A control bit selects input or output mode. In input mode data on the SP pin is shifted into the shift register on the rising edge of the signal applied to the CNT pin. After 8 CNT pulses, the data in the shift register is dumped into the Serial Data Register and an interrupt is generated. In the output mode, TIMER A is used for the baud rate generator. Data is shifted out on the SP pin at ½ the underflow rate of TIMER A. The maximum baud rate possible is 02 divided by 6, but the maximum useable baud rate will be determined by line loading and the speed at which the receiver responds to input data. Transmission will start following a write to the Serial Data Register (provided TIMER A is running and in continuous mode). The clock signal derived from TIMER A appears as an output on the CNT pin. The data in the Serial Data Register will be loaded into the shift register then shift out to the SP pin when a CNT pulse occurs. Data shifted out becomes valid on the falling edge of CNT and remains valid until the next falling edge. After 8 CNT pulses an interrupt is generated to indicate more data can be sent. If the serial data register was loaded with new information prior to this interrupt, the new data will automatically be loaded into the shift register and transmission will be continuous. If no further data is to be transmitted, after the 8-th CNT pulse, CNT will return high and SP will remain at the level of the last data bit transmitted. SDR data is shifted out MSB first and serial input data should also appear in this format.
The bidirectional capability of the Serial Port and CNT clock allows several devices to be connected to a common serial communication bus on which one acts as a master, sourcing data and shift clock, while all other chips act as slaves. Both CNT and SP outputs are open drain with passive pullups, to allow such a common bus. Protocol for slave/master selection can be transmitted over the serial bus, or via dedicated handshaking lines.
1.5.12 Interrupt Control (ICR)
There are five sources of interrupts on the 8520: underflow from timer A, underflow from timer B, TOD alarm, serial port full/empty and FLAG. A single register provides masking and interrupt information. The Interrupt Control Register consists of a write-only MASK register and a read-only DATA register. Any interrupt which is enabled by the MASK register will set the IR bit (MSB) of the DATA register and bring the IRQ pin low. In a multi-chip system the IR bit can be pooled to detect which chip has generated an interrupt request.
The interrupt DATA register is cleared and the IRQ line returns high following a read of the DATA register. Since each interrupt sets an interrupt bit regardless of the MASK, and each interrupt bit can be selectively masked to prevent the generation of a processor interrupt, it is possible to intermix polled interrupts with true interrupts. However polling the IR bit will cause the DATA register to clear, therefore it is up to the user to preserve the information contained in the DATA register if any polled interrupts were present.
The MASK register provides convenient control of individual mask bits. When writing to the MASK register, if bit 7 (SET/CLEAR) of the data written is a zero, any mask bit written with a one will be cleared, while those mask bits written with a zero will be unaffected. If bit 7 of the data written is a one, any mask bit written with a one will be set, while those mask bits written with a zero will be unaffected. In order for an interrupt flag to set IR and generate an interrupt request, corresponding MASK bit must be set.
bit 7 | bit 6 | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
---|---|---|---|---|---|---|---|
IR | 0 | 0 | FLAG | serial | TOD | tim. B | tim. A |
bit 7 | bit 6 | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
---|---|---|---|---|---|---|---|
S/C | × | × | FLAG | serial | TOD | tim. B | tim. A |
1.5.13 Control Registers
There are two control registers in the 8520: CRA and CRB. CRA is associated with timer A and CRB is associated with timer B. The register format is as follows:
Bit | Name | Function |
---|---|---|
0 | START | 1 = start timer A, 0 = stop timer A. This bit is automatically reset when underflow occurs during one-shot mode |
1 | PBON | 1 = timer A output appears on PB6, 0 = normal operation of PB6 |
2 | OUTMODE | 1 = toggle, 0 = pulse |
3 | RUNMODE | 1 = one-shot, 0 = continuous |
4 | LOAD | 1 = force load (this is a strobe input, there is no data storage, bit 4 will always read back a zero and writing a zero has no effect). |
5 | INMODE | 1 = timer A counts positive CNT transitions. 0 = timer A counts 02 pulses. |
6 | SPMODE | 1 = serial port output (CNT sources shift clock). 0 = serial port input (external shift clock required). |
7 | TODIN | 1 = 50 Hz clock required on TOD pin for accurate time. 0 = 60 Hz clock required on TOD pin for accurate time. |
Bit | Name | Function |
---|---|---|
0 | START | 1 = start timer B, 0 = stop timer B. This bit is automatically reset when underflow occurs during one-shot mode |
1 | PBON | 1 = timer B output appears on PB7, 0 = normal operation of PB7 |
2 | OUTMODE | 1 = toggle, 0 = pulse |
3 | RUNMODE | 1 = one-shot, 0 = continuous |
4 | LOAD | 1 = force load (this is a strobe input, there is no data storage, bit 4 will always read back a zero and writing a zero has no effect). |
5, 6 | INMODE | Bits 5 and 6 select one of four input modes for timer B as: CRB6 = 0, CRB5 = 0 – timer B counts 02 pulses. CRB6 = 0, CRB5 = 1 – timer B counts positive CNT transitions. CRB6 = 1, CRB5 = 0 – timer B counts timer A underflow pulses. CRB6 = 1, CRB5 = 1 – timer B counts timer A underflow pulses while CNT is high. |
7 | ALARM | 1 = writing to TOD registers sets ALARM. 0 = writing to TOD registers sets TOD clock. |
2 Electrical Parameters
Stresses above those listed may cause permanent damage to the circuit. Functional operation of the device at these or any conditions other than those indicated in the operating conditions of the specification is not implied. Exposure to the maximum ratings for extended period may adversely affect device reliability.
Characteristic | Symbol | Value |
---|---|---|
Supply Voltage | Vcc | –0.3 V to 7.0 V |
Input/Output Voltage | Vin | –0.3 V to 7.0 V |
Operating Temperature | Top | 0°C to 70°C |
Storage Temperature | Tstg | −55°C to +150°C |
Characteristic | Symbol | Min. | Typ. | Max. | Unit |
---|---|---|---|---|---|
Input high voltage | Vih | +2.4 | – | VCC | V |
Input low voltage | Vil | −3.0 | – | +0.8 | V |
Input leakage current, VIN = VSS + 5 V (TOD, R/W, 02, RES, RS0-3, CS) | Iin | – | 1.0 | 2.5 | µA |
Input resistance (PA0-7, PB0-7, TOD, FLAG, SP, CNT) | Rpi | 3.1 | 5.0 | – | kΩ |
Output leakage current for high impedance state, VIN = 4 V to 2.4 V (DB0-DB7, IRQ) | Itsi | – | ±1.0 | ±10.0 | µA |
Output high voltage, VCC = min., load < −200 µA (PA0-PA7, DB0-DB7) | Voh | +2.4 | – | VCC | V |
Output low voltage, VCC = min., load < 3.2 mA (PA0-PA7, DB0-DB7) | Vol | – | – | +0.4 | V |
Output high current (sourcing), VOH > 2.4 V (PA0-PA7, DB0-DB7) | Ioh | −200 | −1000 | – | µA |
Output low current (sinking), VOL < 0.4 V (PA0-PA7, DB0-DB7) | Iol | 3.2 | – | – | mA |
Output low current (sinking), VOL < 0.4 V (PC, PB0-PB7) | Iol | 13.0 | – | – | mA |
Input capacitance | Cin | – | 7 | 10 | pF |
Output capacitance | Cout | – | 7 | 10 | pF |
Power supply current | ICC | – | 70 | 100 | mA |
Symbol | Characteristic | 318029-02 1 MHz |
318029-03 2 MHz |
||
---|---|---|---|---|---|
min. | max. | min. | max. | ||
02 CLOCK | |||||
TCYC | Cycle time | 1 000 ns | 10 000 ns | 500 ns | 10 000 ns |
TR, TF | Rise and fall time | – | 25 ns | – | 25 ns |
TCHW | Clock pulse width (high) | 440 ns | 5 000 ns | 240 ns | 5 000 ns |
TCLW | Clock pulse width (low) | 440 ns | 5 000 ns | 240 ns | 5 000 ns |
WRITE CYCLE | |||||
TPD | Output Delay From 02 | – | 960 ns | – | 460 ns |
TWCS | CS low while 02 high | 280 ns | – | 255 ns | – |
TADS | Address setup time | 58 ns | – | 20 ns | – |
TADH | Address hold time | 10 ns | – | 10 ns | – |
TRWS | R/W setup time | 58 ns | – | 20 ns | – |
TRWH | R/W hold time | 10 ns | – | 15 ns | – |
TDS | Data bus setup time | 200 ns | – | 75 ns | – |
TDH | Data bus hold time | 15 ns | – | 15 ns | – |
READ CYCLE | |||||
TPS | Port setup time | 300 ns | – | 155 ns | – |
TWCS(2) | CS low while 02 high | 280 ns | – | 255 ns | – |
TADS | Address setup time | 58 ns | – | 20 ns | – |
TADH | Address hold time | 10 ns | – | 10 ns | – |
TRWS | R/W setup time | 58 ns | – | 20 ns | – |
TRWH | R/W hold time | 10 ns | – | 15 ns | – |
TACC | Data access from RS3-RS0 | – | 300 ns | – | 200 ns |
TCO(3) | Data access from CS | – | 240 ns | – | 180 ns |
TDR | Data release time | 50 ns | – | 25 ns | – |
NOTES
- All timings are referenced from VIL max and VIH min on inputs and VOL max and VOH min on outputs.
- TWCS is measured from the later of 02 high or CS low. CS must be low at least until the end of 02 high.
- TCO is measured from the later of 02 high or CS low. Valid data is available only after the later of TACC or TCO.
3.0 Mechanical Requirements
3.1 Marking
Parts shall be marked with Commodore part number, manufacturers identification and EIA data code. Pin 1 shall be identified.
3.2 Packaging
Parts shall be packaged in a standard 40-pin dual-in-line ceramic or plastic package.
APPROVED VENDORS LIST
This page must be detached from the remainder of the drawing whenever this drawing is shown or transmitted to vendors.
Vendors | Vendor Part No. | Commodore Part No. |
---|---|---|
MOS Technology | 8520R3 | 318029-01 |
MOS Technology | 8520R4 | 318029-02 |
MOS Technology | 8520A-1 | 318029-03 |
last updated: September 18, 2020